I. Field of the Disclosure
The technology of the disclosure relates generally to integrated circuits (ICs) and, more particularly, to placement of power gates in three-dimensional (3D) integrated circuits (ICs) (3DICs).
II. Background
Computing devices have become prevalent in modern society. While desktop computing remains widespread, recent years have seen an increase in the number of mobile computing devices. The increase in the number of mobile computing devices is driven in part by their relative affordability and the ever increasing functionality provided on such devices. While the increase in functionality has increased the versatility of the devices, the increase in versatility also increases the drain on the batteries used to power such mobile computing device. In an effort to extend battery life, various power-saving techniques have been implemented, such as putting elements in a sleep mode when such elements are not in use.
Even in sleep mode, some elements within an integrated circuit (IC) may continue to consume power because of stand-by or leakage current of transistors within the IC. One way to reduce such stand-by power consumption is through use of a power gating circuit or power gating cell. The power gating circuit is placed between a power source and one or more downstream logic elements. At its simplest, the power gating circuit is a switch that when turned on, allows power to flow to downstream logic elements, and when turned off, prevents power flowing to the downstream logic elements.
While power gating circuits may be effective at limiting power consumption within an IC, power gating circuits involve a variety of engineering tradeoffs. One such tradeoff is the area penalty imposed by the power gating circuit. An issue conjoined with the area penalty is how placement of the power gating circuit within the IC will impact routing of interconnections between other elements within the IC. Additionally, the power gating circuit has its own power leakage parameters. Accordingly, there need to be additional tools available to circuit designers to improve how power gating circuits are implemented in ICs.